Electronic data translating system



Dec..24, 1957 E. MK. BALDWIN 2,817,480

ELECTRONIC DATA TRANSLATING SYSTEM www Dec. 24, 1957 E. M. BALDWIN ELECTRONIC DATA TRANSLATTNG SYSTEM 5 Sheets-Sheet 2 Filed May 17, 1954 h a 'n Dec. 24, 1957 E. M. BALDwxN ELECTRONIC DATA TRANSLATING SYSTEM Filed May 17, 1954 3 Sheets-Sheet 3 I a .M

fl l /III n 4| 4 ,I A H ZIII 1| .a a af. nllf 2 d z l 5 n M l In s .M n ,r e 5 all. f .u ra ai u IHM 1) u man f y x w MM i w 14m a; L W M. M .0% w m ww ,u um U M.: 1M l MM Mw W4 a un r M72 my y .www M m mw MW, y 2 Mmm www? Z @d United States Patent ELECTRONIC DATA TRANSLATING SYSTEM Ewart M. Baldwin, Los Angeles, Calif., assignor to Hughes Aircraft Company, Culver City, Calif., a corporation of Delaware Application May 17, 1954, Serial No. 430,362

20 Claims. (Cl. 23S-61.7)

The present invention relates to an electronic data translating system, and more particularly to a system for photoelectrically sensing and electronically transforming intelligence placed on data bearing cards or sheets.

The use of individual data bearing cards to record intelligence by means of punches or marks placed thereon has become well established in the accounting iield. Such cards, known as Hollerith or Powers cards, present a number of advantages which have lead to their general acceptance for the storage of information. The development of high speed electronic computing machines, however, has created a need for faster and more ellicient methods of transferring data from punched cards to such computing machines, if the advantages aiforded by the use of cards are to be retained without sacricing the high speed inherent in electronic computation.

While a number of systems have heretofore been utilized for sensing data bearing cards, such systems generally have not been adaptable for high speed, error free operation. For example, prior art systems have frequently employed mechanical elements, such as brushes or levers, to sense the punch marks on the cards. Such elements, due to mechanical inertia and friction, are severely limited as to maximum speed of response. In addition, owing to the complexity of the sensing devices employed, it has been uneconomical to sense the cards more than once during each passage. The prior art systems also have generally required that the card moving means hold the card in a precise position during sensing in order to accurately identify the particular column being sensed. This requirement has been met, for example, by inhibiting the motion of the card during the sensing interval, or by rigidly coupling the card to the card moving means in a predetermined position. In either case the requirement severely limits the maximum speed at which cards may be sensed.

The present invention, on the other hand, overcomes the above and other disadvantages of the prior art systems by providing a self-synchronizing high speed electronic data translating system which includes a number of features to provide essentially error-free operation. According to the basic concept of the invention, cards to be sensed are fed endwise to the system, and are sensed while in motion by a unique photo-diode matrix which includes means for initiating and discontinuing the sensing function, and a plurality of reading stations for successively sensing each column of data on the cards at each reading station. The data sensed by each reading station is then compared with the data sensed at the other reading stations to indicate the identity or nonidentity of the compared data, non-identity serving to indicate that an error or malfunction has occurred.

The card feeding means of the system is synchronous ly interlocked with the electronic sensing elements of the system by synchronizing signals which are generated as a function of card displacement through. `the system.

Accordingly, irregularities in the speed of card feed are automatically compensated for. In addition, cards may be entered into the system at random or at closely spaced intervals, since the initiation and discontinuance of card sensing is a function of means independent of the card feeding mechanism. Accordingly, the system is inherently a self-synchronous high speed device.

The data translating system of the present invention also includes means for converting the sensed data into codes other than the card punch code, these means being essentially independent of the sensing components of the system.

Still another novel feature of the system is that the card sensing operation takes place in a fraction of the interval during which the card is in sensing position. Accordingly, the system has a high tolerance with respect to the actual position of the card at the moment the data in any column is being sensed. The system, therefore, is highly tolerant of the usual irregularities in the size and position of the cards and their punchings, as well as of card slippage and flexing within the card feeding mechanism.

Accordingly, it is an object of the present invention to provide a self-checking system for receiving individual data bearing cards, and for sensing and checking the data punched or marked thereon to provide electronic output signals representing the sensed data.

Another object of the present invention is to provide an electronic data translating system for randomly receiving conventional punched or marked cards, sensing the data punched lor marked thereon, and providing electrical output signals representing the sensed data.

A further object of the present invention is to provide a high speed system of the class described wherein the sensing operation is performed sequentially on a plurality of cards while the cards are in motion.

A still further object of the present invention is to provide a system of the class described wherein the sensing operation is performed by a unique photo-diode reading matrix which includes sensing means for initiating and discontinuing the data translating function ot' the system, and a plurality of data sensing stations for successively sensing each column of data on the cards at each sensing station, and providing a corresponding plurality of sets of output signals representing the sensed data.

A still further object `of the present invention is to provide a system of the class described which includes conversion matrices for the conversion of the data punched or marked on the cards into codes other than the card punch code.

Still another object of the present invention is to provide a system of the class described which includes means for comparing the signals derived from successive sensing of the same data column on the card, and producing an output signal indicating the identity or non-identity of such signals, -thereby indicating errors or malfunctions within the system.

A further object of the present invention is to provide a system of the class described which is inherently designed to tolerate variations in the rate of card feed, card slippage, ilexing, etc., without introducing errors lin the output signals from the system.

The novel features which are believed to be character'4 istic of the invention, both as to its organization and method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which an embodiment of the invention is illustrated by way of example. It is to be expressly understood, however, that the drawings are for il c) the purpose of illustration and description only, and are not intended as a definition of the limits of the invention.

Fig. l is an overall diagram of the system of the present invention;

Fig. 2 is another diagram of the system of Fig. l, illustrating certain elements of the system in greater detail;

Fig. 3a is a diagram of a portion of a typical data card upon which the data translation operation of the present system may be performed;

Fig. 3b is a Schematic diagram of the code conversion matrix of the present invention;

Fig. 4 is a schematic diagram of the comparison circuit of the present invention; and

Fig. 5 is a timing diagram illustrating the operation of the system of the present invention.

General description Turning now to the drawings, wherein like ligures refer to the same or similar elements in the several views, there is shown in Fig. l. a pictorial diagram of the electronic data translating system of the present invention. As shown in Fig. l, the system includes three basic elcments, namely, a card sensing station 7.o for sensing the data on the cards, an electronic control circuit lllll for generating output control signals, and an electronic translating circuit all!) operable in response to the output control signals for converting the sensed data to electrical output signals. The function of card sensing station is to receive individual cards, to move the cards through the station, to sense the data marked or punched thereon, and to generate control, data, and synchronizing signals in accordance therewith. The control signals generated by sensing station lll are supplied to electronic control circuit lll@ which in turn, generates supplies output control signals to electronic translating circuit dill). Electronic translating circuit receives data and synchronizing signals from card sensing station lll, and, operating under the control of the synchronizing signals from the sensing station and the output control signals from electronic control circuit lllll, translates the sensed data signals into output signals representing data marked on the cards.

More particularly, card sensing station lill is designed to receive marked or punched cards, similar to those shown in Fig. 3a, and includes a mechanical card transport device ll for moving the cards, a photo-diode reading and control matrix l2, shown in more detail in Fig. 2, for sensing the data on the cards, and a synchronizing signal generating device l5, coupled to card transport device ll, for supplying synchronizing or clock signals to the system. Photo-diode reading and control matrix l2 produces rst and second sets of data signals representing the data on the cards, and first and second control signals in response to the of the leading and trailing edge, respectively, of a card. Electronic control circuit lille receives control signals from diode matrix .l2 and synchronizing signals from synchronizing signal generating device i3 and produces output signals which control the operation of electronic translating circuit dbd. Electronic translating circuit Mill receives the sets of data signals from diode matrix l2, converts the signals to a preferred code utilizing conversion matrices shown in greater detail in Fig. 3b, and, operating under the control of the signals from control circuit lili), compares the sets of converted data signals and produces output signals representing the data marked on the cards and a signal indicating the result of the comparison operation.

In order to present a complete description of the electronic data translating system of this invention, each of the three basic elements will now be described in detail. In the description which follows, each element will be described in structural detail with reference to Fig. l and the following detailed figures. Upon completion of the structural description, the operation of the system will be described with reference to the composite waveform diagram of Fig. 5.

Card senSlzg station As set forth above, card sensing station lll includes a card transport device ll, a photo-diode matrix l2, and a synchronizing signal generating device ld, and is dcsigned to produce synchronizing signals and data and control signals in response to the passage of a card therethrough. The card transport device includes two pairs of feed rollers and l5 and is designed to receive a data bearing card such as that shown in Fig. 4, edgewise first, and move the card through the station so that the card passes photo-diode matrix l2 column by column, according to the conventional terminology. .Feed rollers and l5 are driven continuously at a uniform rate by a drive motor, not shown.

Synchronizing signal generating circuit i3 is mechanically coupled to one of the feed rollers and provides a plurality of uniformly spaced synchronizing pulses wher the card transport device moves a card forward one column width, where a column width is defined as the width of a punch mark plus one adjacent space. According to one preferred embodiment of the invention synchronizing signal generating device 13 produces four uniformly spaced synchronizing pulses per column width. lt should be understood, however, that any other number of pulses, as for example, 6 or 8, may be used if appropriate modification of the associated electronic circuitry is made.

More particularly, as shown in Fig. l, synchronizing signal generating device includes a synchronizing wheel lo, mechanically coupled to card feed roller pair l5 by means of a shaft l', and having a plurality of uniformly spaced radial slots 18 cut into the edge thereof. A source i9 of illumination and a photo-diode Ztl are arranged on opposite sides of the synchronizing wheel so that the light from light source falling on photo-diode 2li is periodically interrupted by synchronizing wheel 16 and a pulse output signal is produced by photo-diode Zd as each of slots 18 passes between light source ll and photodiode Zll. The diameter of the feed rollers and the number of slots in synchronizing wheel lo are so selected that an integral number of slots pass photo-diode 2G when the feed rollers move the card forward one column width, the integral number of slots being Athe desired number of pulses per column width. rl`he output circuit of photo-diode is connected to the input circuit of a blocking oscillator 2l which is responsive to the applied input pulses to produce a corresponding number of output pulses of the desired waveform, one output pulse being generated upon the application of each input pulse.

It should be noted that while card feed rollers ll; and l5 rotate continuously, a particular card may be entered into the system at any time and accordingly, there is no xed relationship between the leading edge of the card and the generated synchronizing signals. However, Once a card is entered into the system, it is firmly gripped by the feed rollers and, as the card moves forward, synchronizing signals are generated as a direct function of card displacement. Minor variations in card drive speed introduce corresponding variations in the frequency at which the synchronizing signals are generated, thereby maintaining synchronisrn between the card motion and the synchronizing signals until the card is ejected from the card transport device.

Photo diode reading and control matrix It has been set forth previously that card sensing station lll includes a photo-diode reading and control mt,- trix 12 which has a plurality of photo-diodes for producing control and data signals in accordance with the transmission or reection of light by the cards. As shown in greater detail in Fig. 2, the matrix includes a start diode 22 for producing a start signal to initiate the generation of control signals by the -electronic control circuit, first and second reading stations 23 kand 24, respectively, for producing data signals in accordance with the data on the card, and a stop diode 25 for producing a signal to discontinue the generation of control signals by the electronic control circuit.

More specifically, each of reading stations 23 and 24 comprises a plurality of reading photo-diodes, one diode being provided for each data row on the card. The diodes of each reading station are arranged to simultaneously sense one ldata column on the card, reading station 23 being the first reading station to sense a particular row of data as the card is moved through the system. Start diode 22 and stop diode 25, on the other hand, are arranged to generate signals only in response to the passage of the leading and trailing edges, respectively, of the cards. Accordingly, each of these diodes is positioned so that the portion of the card which passes it is an area which includes no punched data.

The relative positions of the start and stop diodes and the first and second reading stations are determined by the distance between the leading edge of the card and the first column of data, and the distance between the trailing edge of the card and the last column of data. The relative positions of the first and second reading stations are, however, a function of the electrical design of the system, and the reading stations may, therefore, be disposed with respect to each other in a preferred manner.

Considering now these relative positions, start diode 22 is positioned with respect to first reading station 23 so that the leading edge of the card is sensed by the start diode as soon as the first data column is in sensing position before the first reading station. Similarly, stop diode 25 is arranged with respect to second reading station 24 so that the diode senses the trailing edge of the card when the last data column is in sensing position before the second reading station.

While the relative positions of the start and stop diodes with respect to the reading stations are determined by the geometry of the cards to be sensed, the relative positions of the reading stations with respect to each other is preselected as a function of the system. More specifically, two reading stations are included within the system to sense the data twice to provide a self-checking system which compares the data sensed by each station. The photo-diodes may be arranged so that both reading stations sense the same data column simultaneously, with the diodes corresponding to a particular row laterally displaced so that each diode senses a different portion of the punched hole, ln this manner, errors caused by defective punching and tears or breaks in the cards may be detected. On the other hand, the diodes may be arranged so that the data in a particular column is sensed by first one reading station and subsequently by the other reading station. The lateral displacement feature between diodes arranged to read punched holes following in the same row may be retained in such an embodiment, while the respective reading stations may be linearly displaced to provide a discreet interval between the sensing of a particular data column by the first and second reading stations, respectively.

According to one preferred embodiment of the in vention, first and second reading stations 23 and 24 are displaced one column width from each other, where a column width is defined as a punch width plus one adjacent space width. When displaced in this manner the first reading station will sense a first data column at the same instant in time that the second reading station is sensing an adjacent data column. When mechanized inthis manner, the output signals from the first reading station may be delayed in time by an appropriately introduced delay circuit to provide for the comparison 6 of the two sets `of lsensed data at a particular interval in time. As will be later shown, the pulse sensing feature of the present invention makes the system readily adaptable to provide for such a delay.

According to another preferred embodiment of the invention, the first and second reading stations are displaced an integral fraction of a column width from each other. Preferably, the fraction of a column width selected should correspond to the time spacing between an integral number of synchronizing pulses as produced by the synchronizing pulse generating wheel. When mechanized in this manner, use may be made of an appropriate one of the synchronizing pulses to sense the proper reading station output signal set. According to such a mechanization, additional delays within the system may or may not be necessary, depending upon the time interval through which the desired signals are available.

For example, if the system provides four synchroniz ing pulses per column width and the reading stations are displaced three-quarters of a column width apart, the first pulse corresponding to a particular column may be used to sense the first reading station While the fourth pulse may be used to sense the second reading station, the first pulse of the succeeding column being utilized to generate a comparison signal indicative of whether the same data has been read by the two reading stations. The mechanization of the electronic control cir cuit to provide for such a mode of operation will be discussed in greater detail hereinbelow.

Electronic control circuit Electronic control circuit receives signals from start diode 22 and stop diode 25 of matrix 12, and synchronizing signals from synchronizing signal generating device 13, and produces output control signals for controlling the response of electronic translating circuit 400 to applied data signals. More particularly, as shown in Fig. 2, electronic control circuit 100 includes a scaleof-four counter 101 for cyclically producing output con trol signals on its four output leads in response to applied synchronizing pulses, a column count flip-flop or bistable element 102 for producing a comparison control signal QM, and a start-stop bistable element or Hip-flop 103 which initiates, and, in conjunction with count flip-flop 102 discontinues, the cyclic operation of scale-of-four counter 101.

More specifically, scale-of-four counter 101 cyclically produces control signals on its four output leads in response to synchronizing pulses when start-stop flip-flop 103 is set to its start state by a signal from start diode 22. Since the synchronizing signals are maintained in accurate synchronism with the motion of the card through the system, the control signals are similarly maintained in synchronism, the four control signals being repeated in sequence as the card moves forward through the system.

As will be understood from the previous discussion, in the embodiment of the invention wherein the first and second reading stations are displaced apart one column width, data signals from the second reading station for the first data column on the card are not available until the second data column is before the first reading station, or until the second cycle of scale-of-four counter 101. Since the comparison function of the electronic translating circuit cannot be performed until data signals are available from both reading stations, count fiip-liop 102 is included within the system to provide a comparison control signal which defines the interval during which the comparison function may be carried out.

Similarly, it will be understood from the previous discussion that the sensing of the last data column on the card by the second reading station is performed during the (n+1)th column width interval, where n is the number of column widths, or data columns, in the data-bearing area of the card. ln order to provide that the scaleof-four counter go through (n-l-l) complete cycles, and then return to its initial state, the discontinuance of cycling by scale-of-tour counter lill is controlled oy the setting of start-stop tlip-flop ltl to its stop state in response to signals from stop diode 25, and the setting of count flip-flop lllZ to its non-compare state.

Referring again to Fig. 2, there is shown a block diagram of one embodiment of the electronic control circuit of the present invention, wherein the desired response is achieved by appropriate interconnection of the respective elements of the circuit. As shown in Fig. 2, count flipop lili?, is a bistable element having two input terminals, designated l' and K respectively, and is responsive to signals applied to either of its input terminals to set to a corresponding stable state, which may be designated the l and 0 states, respectively. Flip-flop itil has two output terminals, designated (2102 and Qm, upon which signals having a relatively high voltage level appear when the ip-tlop is in its l and O states, respectively. The signal appearing on each output terminal is of relatively low voltage level when the bistable element is not in the corresponding stable state. in accordance with well known practice, count tlip-lop .lllZ may conveniently be a conventional Eccles-lordan multivibrator.

Start-stop flip-ilop .HB3 similarly has two input term-inals, designated i103 and Km, and two output terminals, QMS and @103, and is responsive to applied input signals in a manner similar to tiip--op db2. The output circuit ot start diode 22 is connected to apply input signals to the I input of flip-liep ltl, through a start blocking oscillator loll), while the output circuit or stop diode 25 is connected to apply input signals to the K input oi dip-liep ltl through a stop blocking oscillator 101i.

Scale-ol-four counter lill includes a pair of flip-flops Md and ldd, each having two input terminals, designated im, Kw4 and 5195, E105., respectively, end two output terminals, designated QM, Qms and (2105, (2105, respectively, and being responsive to applied input signals in a manner similar to that of `liip-iiop i915. Each of bistable elements ldd and IitlS additionally responds to the simultaneous application of input signals to its l and K input terminals to change its setting from one to the other of its stable states.

The interconnection ci flip-flops to2, 3&3, and lltl to provide the desired response and output signals from scale-of-four counter lill may be made most conveniently by means of logical and and or gates, in accordance with the logical Boolean equations,

where the right hand member of each equation defines the conditions under which an input signal is applied to the llip-'lop input terminal speciiied by the left member of the equation, the indicated mathematical operations being logical, the -lsymbol representing the logical or connective, the adiunction of dissimilar signal symbols implying the logical and connective, and the symbol Cp representing synchronizing or clock pulses.

Such equations may, as more fully discussed in copend.- ing United States application for patent, Serial No. 394,441, entitled Electronic Magnitude Comparator, by Robert Royce iohnson, tiled November 25, 1953, be readily mechanized by employing diode logical and and or gates, such as those shown at pages 5 ll through 514 of an article entitled Diode coincidence and mixing circuits in digital computers, by Tung Chang Chen, in Proceedings of the l. il. E, for May, i950. For eX- ample, Equation l may be mechanized by means of a pair of two-input logical and gates, the (2105 and Cp signals being applied to the two inputs of each gate, respectively, While the outputs of the gates are connected to the I and K input terminals of dip-flop 164. The

' iirst or s; 0 U 0 l (3) 1 O (4) l l whenever start-stop liip-liop 103 is set to its 0, or start state, and returns to and remains in its initial or 00 state if (Q103-|-Q102)=0 following the fourth count.

Accordingly, output signals of relatively high voltage level corresponding to each of the four stable states ot counter lill may oe taken from the counter by means of a gating matrix mechanized according to the logical Boolean equations where V1, V2, V3, V4 designate the output leads upon which the signals appear when the conditions specitied are satisfied.

Ordinarily, if stop diode Z5 is positioned to produce a stop signal when the last data row is in sensing position before the second reading station, start-stop flip-flop 103 will be set to its stop state during the iirst or second count of the linal cycle of scale-ot-four counter lidi, thereby causing Qms to fall to its low level or 0 value during the second count. ln order to provide that (Qm-l-Qm) does not equal (l until the scale-o-our counter has completed its count cycle for the (1H-Util cycle, the inputs to column count flip-flop lili?. are mechanized to provide that the flip-liep romain in its l state until scale-of-four counter lill has passed to its fourth count, and be set to its state by the synchronizing pulse which occurs when V4=l. Since use is also made of signal Qwg as a comparison control signal, the inputs to liip-op M2 are additionally mechanized to provide that the llip-liop be rst set to its l state at the beginning ot the second cycle of scale-of-four counter lol.

The mechanization of the inputs to flip-dop MP2 to provide the desired response may be expressed in accordance with Boolean logical notation as:

K1o2=lQiosV4lCP Electronic translating circuit As shown in Fig. l, translating circuit do@ includes a pai:

of similar reading channels All@ and ill for receiving data signals from the first and second reading stations, respec4 tively, and for translating the signals into output signals representing the sensed data; and a comparison network 4t2 for comparing the output signal from reading channels lltl and 4M and indicating the results of the comparison.

More specifically, as shown in Fig. 2, reading channels d10 and lll include code conversion matrices 420 and 421, respectively, for converting the coded signals pretrol signals from control circuit 100 for producing Voltage. 5

level output signals representing the sensed data.

As shown in Fig. 2, each of reading stations 23 and 24 includes a photo-diode for each row of data on the card, and, therefore, for the conventional l2-row card, there will be 12 photo-diodes for each reading station. Accordingly, the output signals produced by the reading station are in 12bit form. While it would be possible to sense and record these signals directly in l2-bit form, the present system provides that the output of translating circuit 400 be in six-bit alpha-numeric code form. A prel terminals La, Lb, Lc, Ld, Le, andLL, for presenting signals representing the sensed data.

The input signals corresponding to a particular card column appear at the 12 input terminals simultaneously, a punched area of the card producing a signal of relatively high voltage level on the corresponding input lead. while an unpunched area of the card produces a signal of relatively low voltage level. The logical gating matrix is mechanized to respond to the applied input signals in accordance with the logical Boolean equations:

ferred code which has been found especially suitable for Ld 4+5+6+7 (12) use with the conventional IBM card punch code and the Le=2l3l5l7l system ofthe present invention 1s: (0+1{-2+3+4+5+6+7+8+9) (13) 12-1311 6-B1t IBM Code Converted Code Print Character X Y o 1 2 3 4 5 6 7 s 9 a b e d e 1 o 0 1 o 0 o 0 o o o o o 0 0 0 0 o 0 0 0 0 1 0 0 0 o 0 0 0 0 0 o o 0 o 1 0 o 0 0 1 o o 0 o o o 0 o o 0 0 1 o 0 0 0 0 0 1 0 0 o 0 o 0 o 0 0 o i 1 o o o o 0 o 1 0 o o o o o o o 1 0 0 0 o o o 0 o 0 1 o 0 o o o o o 1 0 1 o 0 o 0 0 o o o 1 o 0 o 0 o 0 1 1 0 0 o 0 0 0 o o 0 o 1 o 0 o o 0 1 1 1 o o 0 0 0 o 0 o 0 o 1 o o o 1 0 0 o o 0 0 o o 0 o 0 0 o 0 1 o o 1 o 0 i o 1 o 1 0 0 .o o o o 0 0 o 1 o o 0 1 `o 1 o 0 1 0 o o o o o 0 0 1 o o 1 o o 1 0 0 0 1 0 0 0 o o o 0 1 o o 1 1 o 1 o o 0 .o 1 o o o o 0 0 1 n 1 o 0 o 1` o k0 o 0 o i o o 0 0 o 1 0 1 o 1 o 1 0 0 0 0 o 0 1 o 0 0 0 1 o 1 1 0 0 1 0 0 0 0 o n 0 1 0 o o 1 0 1 1 1 o 1 o o 0 0 o o 0 0 1 o 0 1 1 0 o 0 o 1 o o o o o o o o o 1 o 1 1 0 o 1 1 0 0 1 0 o 0 o o 0 0 0 1 0 0 o 0 1 1 o 0 0 1 0 0 0 o o 0 o 1 0 0 o 1 o 1 o o o 0 1 o 0 0 0 o 0 1 o o 0 1 1 1 0 o 0 o o 1 0 0 o o 0 1 o 0 1 o 0 1 o o o o o o 1 o o 0 o 1 o o 1 0 1 1 o 0 0 0 0 o 0 1 o o o 1 0 o 1 1 o 1 0 o 0 o o 0 o 0 1 o o 1 o 0 1 1 1 1 o o o 0 o o o 0 o 1 0 1 0 1 o o o 1 o 0 o 0 0 0 o o o o 1 1 0 1 o 0 1 o 0 1 o 1 0 o o o o 0 o 1 1 o o 1 0 0 o 1 o o 1 o o 0 0 o o 1 1 0 o 1 i o o 1 o o 0 1 o o o o o 1 1 o i 0 0 c o 1 0 o 0 o 1 o o o o 1 i o 1 o 1 o o 1 0 0 0 o o 1 o 0 o 1 1 0 1 1 0 0 0 1 0 o o o o o 1 o 0 1 1 o 1 1 1 o 0 1 0 o o o o 0 o 1 0 i 1 1 o 0 0 o o 1 0 0 0 0 0 0 o 0 1 i 1 i 0 0 1 Blank o o 1 o 1 o o 1 0 o o o o o 0 o o o o 1 1 o 1 0 1 o o `o o o 0 0 o o o o 1 0 1 o 1 0 o 0 1 1 0 0 o o o o o 0 1 1 o 0 0 1 o o o o 0 1 0 o o o 1 o 0 0 1 o 1 1 o 0 0 0 0 0 1 o o o 1 0 0 o 1 1 o 0 o 1 o o 0 1 o o o o 1 o o 1 1 o 1 i 0 1 o 0 0 o 1 o 0 o 1 0 0 1 1 1 0 o 1 0 0 0 0 1 o o o o 1 o 1 0 1 o 1 1 1 0 o 0 o o 1 o o o 1 0 1 o 1 i o 0 o o 1 o 0 1 0 0 o 0 1 o 1 1 1 0 1 1 0 0v 1 o 0 0 1 0 0 0 1 o 1 1 1 1 0 0 As w1ll be readily understood, the required circuitry Lf=1+3|5+7+9 (14) for translating circuit 400 may be considerably simplified if the desired code conversion is carried out prior to further signal translation. Accordingly, the signals from the first and second reading stations are fed directly to conversion matrices 420 and 421.

One form of conversion matrix 420 for carrying out the conversion according to the above code is shown in Fig. 3b, together with a card illustrating the punching of a particular symbol of the 'code which is read (Fig. 3a). As shown in Fig. 3b, conversion matrix 410 includes a plurality of input leads, X, Y, and 0 through 9 for receiving output signals from the photo-diodes associated with the corresponding card rows, respectively,

Where the right hand member of each equation deines the conditions under which a signal of relatively high voltage level appears on the corresponding output lead, the indicated mathematical operations being logical, the symbol representing the logical or connective, the adjunction of dissimilar symbols implying the logical and connective, and the super bar indicating the complementing of the term covered by the bar. These equations may be mechanized in a manner similar to that discussed hereinabove for the control circuit equations. Conversion matrix 421 may be identical to matrix 420.

The operation of the conversion matrices may be better a logical gating matrix :99, and a plurality of output 75 understood byconsidering the response of thefmatrix to a particular set of input signals. For example, the asterisk symbol, as shown in Fig. 3a, is indicated according to the conventional IBM punched code by a punch mark in the X, 8, and 4 positions of a particular column. The sensing of such a column will produce l or highlevel signals on the X, 8, and 4 input leads, and 0 or lowlevel signals on the remaining input leads; accordingly, the response of the matrix will be Lb=0 Le:

which is the six-bit code group adopted for the asterisk symbol.

lt should be noted that the signals which appear the output terminals of conversion matrices and do not distinguish between data bearing and non. bearing portions of a card passing through the system. For example, the signals appearing at the output terminals when an area between data columns is sensed is identical to the signals appearing when an unpunched or blank data column is sensed. It will be understood from the previous discussion, however, that the synchronizing and control signals do uniquely dene intervals during which data signals appear at the conversion matrix output terminals. Accordingly, use may be made of an appropriate control signal for selecting a synchronizing pulse to sense the output of the conversion matrix and set 'up the reading iiip-op to indicate 'the sensed data.

Returning now to Fig. 2, each of the reading hip-flop sets d3@ and 431 includes six bistable elements, which may be similar to the Eccles-Jordan multivibrators heretofore described. The input circuits associated with each set of tlip-ops are designed to provide that these iiipflops be set to an initial state prior to the presentation ot signals corresponding to a particular data column on the card, and that the ilip-iiop be set to indicate the converted data signals during the interval in which such signals are presented at the output of the conversion matrices.

According to one preferred embodiment of the invention, wherein the irst and second reading stations are displaced one column width, the input circuits to reading flip-dop sets 430 and 431 may be mechanized to provide that the flip-flops be set to their 0 or initial state by the synchronizing pulse which occurs during the int il that signal V1: l, and that the flip-Hops be set in acc dance with the data signals presented oy their respec.,ive conversion matrices by the synchronizing pulse occurs during the interval V2:

rEhe above response may be achieved by mechanizing the inputs to reading flip-flop set 439 according to the logical equations where the logical equations have the significance heretor'ore noted. These equations may be mechanized in a manner similar to the previously discussed logical equations. For example, Equation l6 may be mechanized by means of a three-input logical and gate, the fa-nd" gate being responsive to the application of input signals to all of its inputs for producing an output signal on its output terminal. The inputs of the gate are connected to receive the La data signal, the V2 control signal, and the synchronizing pulses, respectively, while the output terminal is connected to the .la input terminal of reading set 430. The remaining inputs may be mechanized in a similar manner.

The inputs to reading flip-flop set 431 may be mechanized in accordance with a similar set of equations, using the output signals from conversion matrix 421 as the data signals for the input gates.

lt should be noted that output signals corresponding to a particular data column on the card appear at the output terminals of reading lip-ilop set 431 one column width in time later than the same signals appear at the output terminals of reading set 430. In order to provide that the signals corresponding to a particular data column be available during the same time interval so that the comparison operation may be carried out, the signals from reading tiip-op set 430 may be delayed by means of an appropriately introduced delay circuit. The pulsed gating scheme of the present invention lends itself particularly to the use of an additional set of conventional Eccles-jordan multivibrators as such a delay circuit.

Accordingly, as shown in Fig. 2, reading channel 410 includes an additional set 432 of storage flip-Hops for receiving input data signals from the output circuits of reading set 430, and for storing these signals for one column width interval in time. More particularly, storage Lip-iop set 432 includes six bistable elements, one for each of the bistable elements in reading set 43d. The input circuits associated with each Hip-liep receive input signals from the output circuits of the corresponding llipiiop in set 430, synchronizing pulses and the V4 control signal, and provide that the iiip-op be responsive to such signals to set to the state of the corresponding tlip-op in set during the interval that signal V4: l.

The `above response may be provided by mechanizing the input circuits of each flip-flop in set 432 in accordance with the logical Boolean equations,

K=lQxV4lCP (23) where I and K are the input terminals for the particular flip-op in set 432, and Qx and Qx are the output signals from the corresponding flip-liep in set 430. lt should be noted that under the above mechanization of the inputs to storage set 432, there is no provision for returning the flip-flops to an initial state between thc applic"- tion of successive input data signals to the iiip-ops, and accordingly, the output signals from the ip-ops are of a full column width duration.

As will be described in more detail hereinafter', the output signals from flip-liep sets 431 and 432 may be applied to a comparator network to determine the fidelity of the card reading operation for the particular column of data duplicated in these sets. In addition, the output signals from flip-flop set 432 may be directly utilized in conjunction with the signals from iiip-op 164i to form a signal directly recordable according to the Manchester system of magnetic recording, utilizing a system similar to that shown in copending United States patent application, Serial No. 460,965, entitled Magnetic Writing Circuits, by D. L. Curtis, filed October 7, 1954.

It may be recalled that according to another embodiment of the invention, the first and second reading stations may be displaced one quarter of one column width apart. Assuming that this is done, the inputs to reading flip-liep set 430 may be mechanized as set forth by Equations l5 through 21, while the inputs to reading iiip-flop set 431 may be mechanized in accordance with the logical equations,

JFLAT/QCP (30) where the logical equations have the significance heretofore noted.

It will be recognized that when llip-op set 431 is mechanized in accordance with these equations, output signals corresponding to the same data row are presented at the output terminals of ip-iiop sets 430 and 431 during the interval when signal V4=1. Accordingly, no additional delay, such as that previously provided by ip-flop set 432, need be introduced prior to the comparison of such signals during this interval.

Comparison network Comparison network 412 is included within electronic translating circuit 400 in order to provide a self-checking feature for the system by comparing the output signals from reading channels 410 and 411 to indicate the identity or non-identity of the compared signals. Referring now to Fig. 4, there is shown a block diagram of one form of the comparison network which may be employed with the present invention. As shown in Fig. 4, comparison network 412 includes a comparison matrix 440 for receiving voltage level data sign-al sets from reading channels 410 and 411, respectively, and for producing an output signal indicating the identity or non-identity of the received signal sets, and a comparison indicator liip-op 441, responsive to signals from matrix 440, electronic control circuit 100 and to the synchronizing pulses, for indicating the result of the comparison operation.

More particularly, comparison matrix 440 is a diode voltage level gating matrix having first and second sets of input terminals, and being responsive to the simultaneous application of Vsimilar input signals to corresponding input terminals of said first and second sets for producing an output signal. As shown in Fig. 4, matrix 440 includes a first set of input terminals C1, C2, C11 for receiving delayed input signals from reading channel 410, a second set of input terminals C1, C8, C12 for receiving input signals from reading channel 411, and an output terminal C,r for presenting an output signal when corresponding input signals are identical. The structural mechanization of matrix 440 to respond in such a manner may be most conveniently described by means of the logical Boolean equation,

where the terms have the signiicance heretofore noted.

Comparison indicator ilip-op 441, which may be a conventional Eccles-Jordan multivibrator similar to that theretofore described, is normally set to its state except during the comparison interval, when the flip-op is set to its l state if the signals received from reading channels 410 and 411 are identical. If the applied signal sets are not identical, indicator tiip-op 441 remains in its O state throughout the comparison interval, thereby indicating a non-identity and the occurrence of an error or malfunction within the system.

The above response may be provided by mechanizing the input circuits of indicator {lip-flop 441 in accordance with the following logical equations:

J441=CUV3Q102JCP (32) K441=[1]Cp Operation Considering now the operation of the electronic data translating system of the invention, there is shown in Fig.v a composite diagram of the waveforms of electrical signals appearing at various points in the system according to Fig. 2, prior to, during, and after the passage of a data card through card sensing station 10. The waveforms have been` drawn with :amplitudes dis- 14 posed along the vertical axis, and time extending along the horizontal axis.

The system may be placed in operation by applying power to the various elements, and starting the card transport system drive motor. Initially, all of the bistable elements in the System may beg-set to their 0 state by means of a reset mechanism, not shown. Upon setting the system in operation, synchronizing signal generating circuit 13 will produce output synchronizing pulses 31, as shown in Fig. 5. With scale-of-four counter 101 set to its initial or O0 state, output signals Q1114 and 6105 will be at their 1 or relatively high voltage levels 502 and 503, respectively, and V1, which according to logical notation equals (21046105, will also be at its 1 level. Accordingly, the synchronizing pulses will be routed to the K input terminals of the tiip-tlops in reading sets 430 and 431, and the K input terminal of comparison flipflop 441, and these flip-Hops will remain in their 0 states.

At the same time, since both start-stop ip-op 103 and column count flip-flop 102 have been set to their 0 states, output signals Q103 and Q1112 will be at relatively low voltage levels. Accordingly, scale-of-four counter 101 will receive input signals tending to set the counter to its 00 or initial state, and the counter will, therefore, remain in its initial state. Consequently, the V1 control signal produced by electronic control circuit will also remain at its l or high level, and the system will be locked in a stable initial state prior to the receipt of a data bearing card.

Assuming now that a data bearing card is introduced into the card feeding system, the mode of response outlined above will continue until the card is moved into a position such that its leading edge is sensed oy start diode 22, at which time the tirst reading station 23 will also begin to sense the tirst data column on the card. The sensing of the leading edge of the card by start diode 22 causes output signal 5'7 from the photo-diode to fall from its high value 58 to a low value 59, as shown in Fig. 5, this change of signal level in turn triggering start blocking oscillator 1010 to produce a negative output pulse 60, which in turn sets start-stop flip-flop 103 to its start state. When in its start state, tlip-iiop 103 produces a 1 or relatively high level output signal 502 on its Q103 output terminal, and the data sensing cycle of the system r is begun.

It should be noted that since a card may be entered into the system at any time, the instant at which the leading edge of the card is sensed by start photo-diode 22, which is illustrated in Fig. 5 by the time l1, may actually occur simultaneously with the generation of a synchronizing pulse, or may occur during an interval between synchronizing pulses. The relative positions of the start pulse and the synchronizing pulses does not, however, affect the overall operation of the system, but results merely in a shift with respect to the synchronizing pulses and the signals initiated thereby, of the control and data signals from photo-diode reading and control matrix 12. Since the first synchronizing pulse following the setting of start-stop flip-flop 103 to its start state will initiate the cycling of scale-of-four counter 101, the time shift due to random entry of the cards into the system will be at most one synchronizing pulse interval, corresponding to one-fourth of a card column width. As will be pointed out in greater detail later, the data signals corresponding to a particular column of data are available from photo-diode matrix 12 for slightly more than two synchronizing pulse intervals. Accordingly, no error is introduced due to the random entry of cards into the system.

It may be recalled that the setting of start-stop flip-liep 103 to its start state initiates the cycling of scale-of-four counter 101. Accordingly, the rst synchronizing pulse following the setting of flip-Hop 103 to its start state will set the counter to its 0l state. Withl ip-tlop 104 in its o stare {5104:1) and atp-sop iss in its 1 stare rompi), the conditions for 172:1 will be satisfied, and signal V2 will rise to its l level while signal V1 falls to its 0 level. However, due to the finite time of response of conventional bistable elements, the rst synchronizing pulse will be applied to the various gates of the system before V1 has fallen from its l to level, or V2 has risen to its l level, and therefore the first synchronizing pulse will be gated by the V1 signal to perform the reset function previously described for fiip-fiop set 434) in reading channel dit), as indicated by Equation l5, and for flip-flop set 43ll if it is assumed the photo-diode reading stations are positioned one column width apart.

Meanwhile, the card transport system will continue to move the card forward past photo-diode read and control matrix lf2, and the first sensing station will begin to sense the first data row on the card, producing output signals in accordance with the punching of each of the l2 rows of the card. ln order to simplify the operational description of the electronic data translating system of the invention, only the output signal waveshape for a single photo-diode of the first reading station is shown in 5, it being understood that similar output signals will be produced for each of the remaining photo-diodes of the station in accordance with the data punching for their respective data rows. The waveshape of the signal from the single diode is illustrated in Fig. 5 by the waveform Silo which may also be considered to represent the signal appearing at one of the output terminals of conversion matrix 42u, if it is assumed that the conversion function of the matrix for the particular diode row and output terminal implies a direct connection, if it is assumed, for example, that signal 5th? represents the output signal from the X photo-diode in the rst reading station, it is clear from Equation 9 that signal Silo is also representative of signal l.a from conversion matrix Kilt?.

Returning now to the operation of the system, as shown in Fig. 5 signal 506 will be at a relatively low level S07, corresponding to the scanning1 of an unpunched area of the card, immediately prior to the scanning of the first data column punched on the card. Simultaneously with the generation of start signal dil, the first reading station will begin to sense the first data column on the card. Signal 5%, representing the response to a punched marl: in the first data column, will rise to its relatively high level value as indicated by reference character lt will be recognized that if the sensing photo-diodes of the first reading station are of substantially smaller width than the card punched hole width, signal 56o will rise to its high level sharply. Similarly, since the card punched hole is ordinarily slightly wider than 2/3 of a column width, signal tlt will remain at its rel: ively high level value for slightly longer than two synchronizing pulse intervals.

Accordingly, with Vzz' the second. ctfonizing pulse following the start signal will sense representing a matrix output signal, and set e corresponding flip-flop of reading flip-flop set d3@ to its l state. A similar setting operation will taire place for each of the remaining fiip-fiops in set in accor-dance with their respective input signals. For the salte of simplicity, only the output signal from the flip-flop which received input signal 5% is shown, this signal being labeled Ao cordingly, at the instant of the second synchronizing pulse, signal dill will rise from its O or low level to its l or high level, as indicated in Fig. 5 by the reference characters Sil and SR2, espectively During the interval in which thc first reading station senses the first data column on the card, it is clear that the second reading station will be sensing an unpunched area of the card. Accordingly, signal which represents the output signal for the second reading station photo-diode which correspon-ds to the photo-diode which produces signal 506, will be at a relatively low level 515. It will again be assumed that signal Sid in a manner similar to that described for signal 06, is considered to rep- 16 resent one of the output signals of conversion matrix 421. Since this output signal is similarly at a low level, the corresponding fiip-op in reading set 43T. will not be set to its l state, and its output signal 517 will therefore remain at a relatively low level Siti.

The second synchronizing signal will also set scale-offour counter lill to its l() state, and the V3 output signal will rise to its l level. Ordinarily, use will be made of the third synchronizing pulse during the V 3 signal interval to sense the output of comparison matrix and set comparison flip-flop lli-l accordingly. However, since column count flip-flop 102 is still in its 0 state, its output signal (2102 remains at its low level, designated 52o in Fig. 5. Accordingly, comparison iiip-iiop 42431 will remain in its O state, and its output signal, which is designated by the waveform 5ft@ in Fig. 5, will remain at its low level.

The third synchronizing signal will, in turn, set scalcof-four counter lill to its fourth or 11 state, and V4 will rise to its l level, which in turn gates tne fourth synchronizing pulse to set column count flip-flop (2102 to its l state, producing a relatively high voltage level signal 521 on its Q1@ output terminal. rl`he V., control signal at its high level value will also gate the fourth synchronizing pulse to set each flip-iop in storage set d3?. to the state of its corresponding fiip-fiop in reading Hip-flop set 430. Accordingly, the output signal from the tiip-flop in set which corresponds to the flip-fiop in 43! which produces output waveshape 510, will be set to its l level as indicated by the waveform designated 532.

The fourth synchronizing pulse will also return scaleof-four counter Mil to its initial or 00 state, and the sysv tem will respond to further synchronizing pulses by rcpeating the cycle of operations previously outlined. However, since Qwz has now been set to its l state, the comparison function ot' the system will be carried out during the V3 interval of the second and each succeeding cycle. More particularly, the first synchronizing pulse of the second cycle will carry out the reset functions previously outlined, and also set counter lili to its 0l state, whereat V2=l. Meanwhile, the card being sensed will have moved through the system so that its first data row is now before the second reading station, while its second data row is before the rst reading station. Consequently, the second reading station now senses the row previously sensed by the rst reading station, and signal 5M- Will rise to its l or high level, designated F in Fig. 5. At will be recogi, SSI.

.310 nized that the waveshape of signal SM corresponds, under the assumptions previously noted, to waveshape 506 delayed one column width in time.

The second synchronizing pulse of the second cycle is combined with the V2 control signal in accordance with Equations 16 through 21 to set i lisp set to indicate the second column of data now 1 nsed by the first rcading station, while set 431i is simultaneously set to indicate the first column of data which is now being sensed by the second reading station. waveshape Si, which is representative of the output of flip-flop set @El in the sense heretofore noted, will therefore rise to its l or high level 5l9. It should be noted that signal waveform 517 correspends to waveform Si@ delayed one column width in time.

The second synchronizing pulse of the second cycle will also set counter 10i to its third state, whereat V3=l. Since signal QM is now at its high level, it will. be recognized from Equation 32 that the comparison function of the system will be carried out upon receipt of the next synchronizing pulse. lt will also be recognized that reading set 431 and storage set each have been set to indicate the information gained from sensing the first data column on the card, storage set holding the information as sensed by the first reading station, while reading set 435i holds the information as sensed by the second reading station. it will be recalled that if these two sets of data are identical, comparison matrix 44) will produce a high level output signal CV in accordance 'german with Equation '31. It will be noted from Fig. 5 -that fthese conditions fare satisfied during the interval -of l'the second cycle when signal V3 is l, since both signal :517 and 530 are at'their high levels'519 and '532, respectively. Accordingly, the lthird synchronizing signal is combined with-comparison 'signal Cv, and signals V3 and Q105, in 'accordance with -Equation 32, vand `is applied to the J input of comparison -ip-op ,441 to `set the flip-flop `to 'its 1 state, and thereby cause its output signal `540 to rise to Tits `high level value 541, as-sh'own in Fig. 5, to indicate-comparison.

'Itis clear-that if the output signal Cr of comparison matrix 440 Aremains at its level corresponding to the application of non-identical input signals to the comparison matrix, the third synchronizing pulse will not ybe gated 'to the I input of flip-flop 441, and the nip-flop will remain in its.0 state, Ithereby'indicating that an error or 'malfunctionhas occurred Within the system. `If itis assumed that the data stored in iiip-flopfsets 43-1and 432 Vis identical, the fourth-synchronizing pulse of the second cycle, functions as previously recited to recycle counter l101, and in addition, to resetcornparisonip-op 441 to its `0 state. It will also be recognized that the fourth vsynchronizing pulse may kbe rcombined with the high level output signal from flip-flop 441 `to gate the signals stored ineither ofipafiop sets 43.1 kor 432 to a suitable recording system. The cycle of operations thus outlined will be repeated for each succeeding column of data on the card -until each of thetcolumns of data on the card has been ysensed by Vboth reading stations, and the apjpropriate translation operations performed.

As previously discussed, in Iorder `to complete the 'sensing-cfallcolumns of data on a card by both reading stations, scale-of-four counter 101 must ygo through (n+1) cycles, where n is the number of data columns ont the card. During the (n+1)st cycle, the second reading station `will Vsense the final data column of the card, while `the first `reading station will vsense the vunpunched area of the card between the `last data column vand the trailing edge of the-card. Since the operation of .electronic translating circuit 400 during the inalcycle corresponds to the response previously outlined for the second-cycle, no further description will be made of the operation of this portion of the system.

The response of electronic control circuit 100, however, is modified vduring the .(n+1)st cycle in order to inhibit the further response of the control circuit upon the completion of the cycle and thereby discontinue the ltranslating vfunction of the electronicvtranslating circuit. More particularly, as the last data column on the card is sensed by the second reading station and produces waveshape 580 of signal 514, stop diode 25 `senses the trailing edge of the card, and the output signal 62 ofthe diode rises from a low level 63 to a'high'level 64. This change of signal level in turn triggers stop blocking oscillator 1011 to produce a negative output pulse 61 which resets `start-stop flip-Hop 103 to its stop state, lthereby causing its output signal Qm to fall fromits vl or high level 502 to its 0 or low level 501.

The setting of start-stop vp-op 103 to its stop state t.

will not, however, inhibit the continued response of scale'- of-four counter 101, since,-as will be seen yfrom Equation 2, the .T input of rflip-.hop 105 continues to receive rsynchronizing pulse input signals so-long as either of .signals Qm yor Qm is at its A1 or high level. Accordingly, scale-offour counter 101 responds-to the second, third and lfourth synchronizing pulses of the final cycle by 'setting to its l0, 11, and 00 states, respectively.

With start-stop fiip-'flop 103 in itsO state, its QW output signal will be at a 1 or highlevel, and accordingly, the fourth synchronizing, pulse ofthe final cycle will also be combined with signal'm and signal V4 in accord- Aancewith Equation 8 'to resetfcolumnvc'ount flip-nop "102 toits 0 state, thereby `causingfits ioutput signal -Qm Ito fall toits 0 level 523.

:It .will `thus beseen that both rstart-stop fliplop 103 fand column count Hip-flop 102 'are now in their l0 states, and accordingly, the conditions for the applicationof'synchroniz'ing pulses to the J input of'ip-op '105, as specified by AEquation 2, are nolongersatisfied. Accordingly, `scale-of-four counter 101 will continue toneceive synchronizing pulses only'on the input of flip-flop 105, andxthe 4counter will therefore remain in its 00 or initialstate.

This state, and the state ofall remaining elements fin `the system will be seen to correspond to the initial state previously kdescribed prior to the receipt ofthe first card. Accordingly, lthe `system is now ready toreceive the'next card to be sensed, whereupon the operational-cycle outlined will be repeated.

Whatis claimed as newis:

.1. In anelectronic data translating'system for sensing moving data-bearing cards to produce electrical -output `signals representingthe sensed data in accordance with the displacement of the card through the system, the combination comprising: means for moving a data bearing `card at Vsubstantially constant velocity in a direction defined bythe rows of data on the card, and at right angles .to the columns of data on the card; first and secondreading stations for sensing the 'data vmarked on the cards and producing first kand second sets of Vdata signals for each data column on the card, said -rst and vsecond reading stations `each including a plurality-of sensing-devices displaced in columnar form for simultaneously sensing a plurality of data rows on the cards; means for sensing the relative position -of the 'card to produce a start output signal when the first data column on the `.card `is in sensing position before 4said -first Vreading Istation; vand means for sensing the relative position of the card. to produce a-stop output signal when the last data columnis in sensing position -before said second reading 1station.

2. The combination defined in claim l, including means coupled yto saidcard moving means 'for generating a plu- Arali-tyof substantially uniformly time-spaced synchroniz- `motion of adata card.

4. In an electronic data translating system for photoelectrically .scanning multi-column punched data cards column by column as the card moves 'through the system, and Aproducing electrical output signals representing the sensed data in accordance with the displacement of the card through the system, the combinationcomprising: a card sensing station for scanning a moving data .card column by column, said station including -means lfor vsensing each data column ltwice and producing two sets'of data signals `for each data column on the card, means for sensing the passage of the leading and trailing edge of the card, respectively, and producing control signals in accordance therewith,and synchronizing signal generating means for producing a plurality of uniformly spaced synchronizing signals in accordancewith the displacement ofthe card -one column width `.through the system; an electronic control circuit responsive to lsaid control signals and said synchronizing signals Afor cyclically producinga series of output control signals, one output control signal for each synchronizingsignal; and an electronic translating device including means for converting each set of-data signals to another'set according to a predetermined code, means, responsive to the converted data signals, said synchronizing signals and said output con trol signals, :for producing two sets of voltage levelfoutfp'ut signals representing said sensed data, and means, responsive to said synchronizing signals and said output conanimee trol signals. for comparing said two sets of voltage level output signals and producing an output signal indicating the result of the comparison.

5. The combination defined in claim 4, wherein said electronic control circuit includes a modulo-x counter, where x is the niimher of synchronizing signals per column width produced bv the svnchronizing signal generating means. for counting said synchronizing signals and cvclicallv producing x output control signals, one for each count of the counter: means responsive to the control signal produced bv said leading edge sensing means for initiating the counting of signals bv said counter; and means responsive to the control signal produced by said trailing edge sensing means for locking said counter in its initial state.

6. The combination defined in claim 4. wherein said electronic control circuit includes a modulo-x counter, where x is the number of' synchronizing signals produced by the synchronizing signal generating means per column width, said counter having x output terminals, one for each count of the counter, upon which an output control signal appears when the counter is in the corresponding stable state; first means responsive to said synchronizing signals for advancing the count of said counter one count for each synchronizing signal; second means responsive to said start control signal for rendering said first means operable; and third means, responsive to said stop control signal for rendering said first means inoperable when said counter returns to its initial state.

7. The combination defined in claim 6 wherein said third means is responsive to said stop control signal, one of said output control signals and said synchronizing signals for rendering said first means inoperable after said counter has completed the count cycle during which said stop signal occurs and has returned to its initial state.

8. The combination defined in claim 4, wherein said means for converting each set of data signals to another set according to a predetermined code includes a logical gating network having a plurality of input circuits, including one input circuit for each data row on the card; a plurality of output circuits, including one output circuit for each digit of said predetermined code, and means interconnecting said input and output circuits, said last named means including logical and, or and complementing circuits interconnecting said input and output circuits.

9. The combination defined in claim 4, wherein said means for converting each set of data signals to another set according to a predetermined code includes a logical gating network having twelve input circuits, one for each data row on the card, six output circuits, one for each digit of said predetermined code, and a plurality of logical gates interconnecting said input and output circuits.

l0. The combination defined in claim 9, wherein said plurality of logical gates interconnecting said input and output circuits includes logical and, or and complementing circuits mechanizing the response of said logical gating networks in accordance with the logical equations:

wherein La, Lb, Lc, Ld, Le, and Lf represent the six output circuits, respectively; X, Y, and through 9, represent the twelve input circuits, respectively; the -lsymll. The combination defined in claim 4, wherein said means responsive to the converted data signals, said synchronizing signals, and said output control signals for producing two sets of voltage level output signals representing said sensed data includes two sets of reading fiipflops, each of said sets including one fiip-fiop for each digit of said converted data signal set, said flip-flop having first and second input terminals and first and second output terminals, and being responsive to signals applied to said first input terminal for producing a voltage level output signal on said first output terminal and to signals applied to said second input terminal for producing a voltage level output signal on said second output terminal; means for applying said synchronizing signals, said output control signals and said converted data signals to the first input terminal of the corresponding flip-flop; and means for applying said synchronizing signals and said output control signals to the second input terminals of all of said flip-flops.

l2. The combination defined in claim 4, wherein said means responsive to the converted data signals, said synchronizing signals, and said output control signals for producing two sets of voltage level output signals representing said sensed data includes two sets of reading fiipflops, each fiip-fiop having a first input terminal for receiving a corresponding converted data signal, said output control signals, and said synchronizing signals, a second input terminal for receiving others of said output control signals and said synchronizing signals, and first and second output terminals, and being responsive to signals applied to said first input terminal for producing a voltage level output signal on said first output terminal, and to signals applied to said second input terminal for producing a voltage level output signal on said second output terminal.

13. The combination defined in claim 4, wherein one of said means responsive to the converted data signals, said synchronizing signals and said output control means includes additional delay means for delaying the production of said voltage level output signals, whereby said two sets of voltage level control signals representing the sensed data for a particular row are made available simultaneously for at least one synchronizing pulse period.

14. The combination defined in claim 13 wherein said delay means includes an additional set of tiip-iiops, including one fip-flop for each digit of the converted data set, responsive to the voltage level output signals to be delayed, said output control signals, and said synchronizing signals for producing a delayed setV of voltage level output signals corresponding to the applied set of voltage level signals.

l5. The combination defined in claim 4 wherein said means, responsive to said synchronizing signals and said output control signals for comparing said two sets of voltage level output signals and producing an output signal indicating the result of the comparison includes a logical network for combining each voltage level output signal of one of said sets with the corresponding voltage level output signal of the other of said sets and producing a comparison signal when said corresponding voltage level output signals are identical; a liip-op having first and second input terminals, and being responsive to signals applied to said first and second input terminals to set to a corresponding stable state, and to signals applied simultaneously to both of said first and second input terminals to change the setting of the flip-Hop; first means, responsive to said comparison signal and said output conf SlglalS fOr applying said synchronizing signals to said first input terminal, and second means for applying said synchronizing signals to said second input terminal.

16. rhe combination defined in claim l5, including means for rendering said first means operable when said corresponding voltage level output signals of said two data vsignal sets are signals representing the same data column on the card.

2l 17. The combination defined in claim l5, wherein said logical gating network is mechanized according to the logical formula:

wherein C1 through C6 reepresent a first set of input signals,

C1 through C6 represent the complements of said first set of input signals, respectively; C7 through C12 represent a second set of input signals, C7 through C12 represent the complements of said second set of input signals, respectively; the represents the logical or connective, the adjunction of dissimilar terms implies the logical and connective and the right hand member of the equation defines the conditions under which an output signal Cv is produced.

18. The combination defined in claim 4, wherein said electronic control circuit includes a modulo-four counter, having four output terminals, and being responsive to said synchronizing signals for cyclically producing output control signals on each of said output terminals; and means responsive to said control signals for applying said synchronizing pulses to said counter.

19. In an electronic data translating system for sensing cards bearing data markings displaced in columns and rows, the columns and rows being at substantially right angles to each other, and producing electrical output signals in accordance with the displacement of the data on the card, a reading and control matrix including: a first reading station for sensing the data marked on the cards and producing a first set of data signals representing the sensed data, said rst reading station including a plurality of sensing devices, including one sensing device for each data row on the card, displaced in columnar form for simultaneously sensing a plurality of data rows on the card; a second reading station, displaced in at least one direction with respect to said first reading station, for sensing the data marked on the cards and producing a second set of data signals representing the sensed data, said second reading station including a plurality of sensing devices, including one sensing device for each data row on the card, displaced in columnar form for simultaneously sensing a plurality of data rows on the card; first means for sensing the relative position of the card to produce a start output signal when the first data column on the card is in sensing position before said first reading station; and second means for sensing the relative position of the card to produce a stop output signal when the last data column is in sensing position before said second reading station.

20. The reading and control matrix defined in claim 19, wherein said sensing device of said first and second reading stations is a photoelectric cell.

References Cited in the file of this patent UNITED STATES PATENTS UNITED STATES PATENT OFFICE Certificate of Correction Patent No. 2,817,480 December 24, 1957 Ewart M. Baldwin It is hereby certified that error appears in the printed specification of the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 12, line 38, Equation (23), for K= [QxVQOIB read -K= [QJ/*4] 01,-; column 13, line 53, for theretofore read -l1eretofore-.

Signed and sealed this 1st day of April 1958.

Attest: KARL H. AXLINE, Atestz'ng Oyfioer.

ROBERT C. WATSON, Uommz'ssz'oner of Patents.

UNITED STATES PATENT OFFICE Certificate of Correction Patent No. 2,817,480 December 24, 1957 Ewart M. Baldwin It is hereby certified that error appears in the printed speciiioation of the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Collimn 12, line 38, Equation (23), for K= [QV4]O read -K= [QJ/4] 01,-; column 13, line 53, for theretofore read -heretofore-.

Signed and sealed this 1st day of April 1958.

[SEAL] Attest: KARL H. AXLINE, Attestng Oycer.

ROBERT C. WATSON, ommz'sszoner of Patents. 

